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Wednesday, July 2nd
| 08:20 - 08:40 | Welcome |
| 08:40 - 09:30 | Keynote Talk 1: Security and Ubiquity Opportunities for Application-Specific Processors, Ruby B. Lee |
| 09:40 - 10:30 |
Session 1: Application-Specific Processor Instruction Sets Chair: Dake Liu |
| Fast Custom Instruction Identification by Convex Subgraph Enumeration. Kubilay Atasu, Oskar Mencer, Wayne Luk, Can Ozturan and Gunhan Dundar |
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| Bit Matrix Multiplication in Commodity Processors. Yedidya Hilewitz, Cédric Lauradoux and Ruby Lee |
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| 10:30 -11:00 | Break and Interactive Session 1: |
| Synthesis of Application Accelerators on Runtime Reconfigurable Hardware. Mythri Alle, Keshavan Varadarajan, Ramesh Reddy, Nimmy Joseph, Alexander Fell, Adarsha Rao, S K Nandy and Ranjani Narayan |
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| Floating Point Multiplication Rounding Schemes for Interval Arithmetic. Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan and Oana Boncalo |
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| Fast Multivariate Signature Generation in Hardware: The Case of Rainbow. Sundar Balasubramanian, Andrey Bogdanov, Andy Rupp, Jintai Ding and Harold W Carter |
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| Fault-Tolerant Dynamically Reconfigurable NoC-based SoC. Mohammad Hosseinabady and Jose Nunez-Yanez |
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| Security Processor with Quantum Key Distribution. Thomas Lorünser, Edwin Querasser, Thomas Matyus, Momtchil Peev, Johannes Wolkerstorfer, Michael Hutter, Alexander Szekely, Ilse Wimberger, Christian Pfaffel-Janser and Andreas Neppach |
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| Fully-Pipelined Efficient Architectures for FPGA Realization of Discrete Hadamard Transform. Pramod Meher and J C Patra | |
| Reconfigurable Viterbi Decoder on Mesh Connected Multiprocessor Architecture. Ritesh Rajore, Ganesh Garga, S K Nandy and Jamadagni H S |
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| Run-time thread sorting to expose data-level parallelism. Tirath Ramdas, Gregory Egan, David Abramson and Kim Baldridge |
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| 11:00 -12:15 |
Session 2: System-level Interconnect and Mapping in SoCs Chair: Yvon Savaria |
| A New High-Performance Scalable Dynamic Interconnection for FPGA-based Reconfigurable Systems. Slavisa Jovanovic, Camel Tanougast and Serge Weber |
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| Extending the SIMPPL SoC Architectural Framework to Support Application-Specific Architectures on Multi-FPGA Platforms. David Dickin and Lesley Shannon |
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| PERMAP: A Performance-Aware Mapping for Application-Specific SoCs. A. E. Kiasari, S. Hessabi and H. Sarbazi-Azad |
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| 12:15 - 01:30 | Lunch |
| 01:30 - 02:45 |
Session 3: Advances in Cryptography Chair: Christopher Wolf |
| Low-cost Implementations of NTRU for pervasive security. Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede and S. Berna Ors Yalcin |
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| On the High-Throughput Implementation of RIPEMD-160 Hash Algorithm. Miroslav Knezevic, Kazuo Sakiyama, Yong Ki Lee and Ingrid Verbauwhede |
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| Zodiac: System Architecture Implementation for a High-Performance Network Security Processor. Haixin Wang, Guoqiang Bai and Hongyi Chen |
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| 02:45 - 03:15 | Break |
| 03:15 - 04:30 |
Session 4: New Computational Methods Chair: Georgi Kuzmanov |
| Efficient Systolization of Cyclic Convolution for Systolic Implementation of Sinusoidal Transforms Pramod Meher |
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| Resource Efficient Generators for the Floating-point Uniform and Exponential Distributions David Barrie Thomas and Wayne Luk |
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| Low Discrepancy Sequences for Monte Carlo Simulations on Reconfigurable Platforms Ishaan Dalal, Deian Stefan and Jared Harwayne-Gidansky |
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| 04:30 - 04:50 | Break |
| 04:50 - 06:05 |
Chair: David Thomas |
| A Subsampling Pulsed UWB Demodulator Based on a Flexible Complex SVD. Yves Vanderperren and Wim Dehaene |
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| Dynamically Reconfigurable Regular Expression Matching Architecture. Divyasree J, Rajashekar H and Kuruvilla Varghese |
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| An MPSoC Architecture for the Multiple Target Tracking Application in Driver Assistant System. Jehangir Khan, Smail Niar, Yassin Elhillali, Atika Rivenq-Menhaj and Jean-Luc Dekeyser |
Thursday, July 3rd
| 08:40 - 09:30 | Keynote Talk 2: The Art of Application-Specific Processor Design: Great Artists use Good Tools, Gert Goossens |
| 09:40 - 10:30 |
Session 6: New Directions in Application-Specific Design Chair: Lesley Shannon |
| 9:40-10:30 | High-Level Energy Estimation and Analysis of RF-Powered Devices. Manuel Wendt and Matthias Grumer |
| Managing Multi-Core Soft-Error Reliability Through Utility-driven Cross Domain Optimization. Wangyuan Zhang and Tao Li |
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| 10:30 -11:00 | Break and Interactive Session 2: |
| An Efficient Implementation Of A Phase Unwrapping Kernel On Reconfigurable Hardware. Sherman Braganza and Miriam Leeser |
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| A Parallel Hardware Architecture for Connected Component Labeling Based on Fast Label Merging. Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann and Peter Pirsch |
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| Operation Shuffling over Cycle Boundaries for Low Energy L0 Clustering. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor and Masaharu Imai |
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| An Efficient Digital Circuit for Implementing Sequence Alignment Algorithm in an Extended Processor. Vamsi Kundeti, Yunsi Fei and Sanguthevar Rajasekaran |
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| Concurrent Systolic Architecture for High-Throughput Implementation of 3-Dimensional DWT. Basant K Mohanty and Pramod Meher |
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| Hierarchical Design Space Exploration of a Cooperative MIMO Receiver for Reconfigurable Architectures. Shahnam Mirzaei, Ryan Kastner, Ali Irturk, Brad Weals and Richard Cagley |
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| A dynamic holographic reconfiguration on a four-context ODRGA. Mao Nakajima and Minoru Watanabe |
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| FGPA-based hardware accelerator of the heat equation with applications on infrared thermography Fernando Pardo Seco, Paula López Martínez and Diego Cabello Ferrer |
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| FPGA Based Singular Value Decomposition for Image Processing Applications. Masih Rahmati, Mohammad Sadegh Sadri and Mehdi Ataei Naeini |
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| 11:00 -12:15 |
Session 7: Acceleration of aScientificnd DSP Applications Chair: Joseph Cavallaro |
| Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs. Arpith Jacob, Jeremy Buhler and Roger Chamberlain |
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| A Multi-FPGA Application-Specific Architecture for Accelerating a Floating Point Fourier Integral Operator. Jason Lee, Lesley Shannon, Matthew Yedlin and Gary Margrave |
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| 12:15-1:30 | Reconfigurable Acceleration of Microphone Array Algorithms for Speech Enhancement. Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao Lu, Xiaoxiang Shi and Wayne Luk |
| 12:15 - 01:30 | Lunch |
| 01:30 - 02:45 |
Session 8: Advanced Communications Applications Chair: Praveen Raghavan |
| Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards. Yang Sun, Yuming Zhu, Manish Goel and Joseph Cavallaro |
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| Architecture and VLSI Realization of a High-Speed Programmable Decoder for LDPC Convolutional Codes. Marcos B.S. Tavares, Steffen Kunze, Emil Matus and Gerhard P. Fettweis |
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| 2:45-3:15 | Buffer allocation for Advanced Packet Segmentation in Network Processors. Daniel Llorente, Kimon Karras, Thomas Wild and Andreas Herkersdorf |
| 02:45 - 03:15 | Break |
| 03:15 - 04:30 |
Chair: Lejla Batina |
| New Insights on Ling Adders. Alvaro Vázquez and Elisardo Antelo |
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| Integer and Floating-Point Constant Multipliers for FPGAs. Nicolas Brisebarre, Florent de Dinechin and Jean-Michel Muller |
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| 4:30-4:50 | An Efficient Method for Evaluating Polynomial and Rational Function Approximations. Nicolas Brisebarre, Sylvain Chevillard, Milos Ercegovac, Jean-Michel Muller and Serge Torres |
| 04:30 - 04:50 | Break |
| 04:50 - 06:05 |
Session 10: Interconnect and Mapping Chair: Dirk Stroobandt |
| Mapping of the AES Cryptographic Algorithm on a Coarse-Grain Reconfigurable Array Processor. Andres Garcia, Mladen Berekovic and Tom Vander Aa |
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| RECONNECT: A NoC for polymorphic ASICs using a Low Overhead Single Cycle Router. Nimmy Joseph, Ramesh Reddy C, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S K Nandy and Ranjani Narayan |
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| Loop-Oriented Metrics for Exploring and Application-Specific Architecture Design-Space Maria Mbaye, Normand Bélanger, Yvon Savaria and Samuel Pierre |
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| Banquet and Social Event |