PhD

Process Technology

• Ge and III-V CMOS scaling
• Post-CMOS nano
• Reliability research at imec
• Memories
• Power devices
• GaN Power Converters
• Nanoscale properties of new materials for emerging memory de
• Ion-solid interactions
• Probing semiconductor devices on the atomic scale
• Packaging and interconnection
• SiGe-based MEMS
• RF-MEMS
• Advanced lithography
• Simulation of wafer plating uniformity
• Superfilling of 3D via structures with alternative metals
• Diamond bit cutting for metal bonding

Ge and III-V CMOS scaling

CMOS downscaling driven by Moore's law cannot be met anymore by simply reducing transistor dimensions since material properties such as the carrier mobility start to limit the device performance. The use of alternative materials that exhibit larger mobility such as III-V and Ge as the semiconductor in MOS structures may overcome such limitations. Especially the combination of Ge pMOS devices with III-V nMOS to produce high speed CMOS circuits is a very tempting idea that could revolutionarize the microelectronics industry. However, many barriers still have to be overcome before this idea can be put into reality. Research areas in this domain are: Passivation of gate stacks with low interface state density and high capacitance, device modeling and processing of quantum well Ge and III-V devices for further scaling, doping and contacting schemes to reduce series resistance issues in scaling and defect-free epitaxial growth of Ge and III-V materials into small trenches on silicon wafers.

Responsible scientists: Marc Meuris, Kristin De Meyer, Marc Heyns