PhD

Process Technology

• Ge and III-V CMOS scaling
• Post-CMOS nano
• Reliability research at imec
• Memories
• Power devices
• GaN Power Converters
• Nanoscale properties of new materials for emerging memory de
• Ion-solid interactions
• Probing semiconductor devices on the atomic scale
• Packaging and interconnection
• SiGe-based MEMS
• RF-MEMS
• Advanced lithography
• Simulation of wafer plating uniformity
• Superfilling of 3D via structures with alternative metals
• Diamond bit cutting for metal bonding

Simulation of wafer plating uniformity

Through mask electroplating has become a key deposition technology for the fabrication of micro-electronic components. Typical applications include thick Cu metallization for high current capabilities and solder bump fabrication. However, assuring a uniform thickness of the deposited metal remains challenging due to the many effects involved. Some of the contributing factors are: on wafer pattern distribution, electrolyte employed, applied current density, electroplating tool concept, anode configuration and flow rate of the electrolyte.

Typically, the uniformity of the electroplated layer is considered on several, somewhat arbitrary, length-scales. One regularly used classification consists of wafer scale (>1cm), pattern scale (1cm-100μm) and feature scale (<100μm).

The goal of the project is to establish a FEM modeling strategy to predict thickness distribution across different length-scales, from wafer scale across die scale to individual feature scale. In this, several challenges have to be met:

• Setting up of a FEM framework that is able to deal with the simulations at the different length scales
• The determination of the parameters that are relevant for inclusion in the model
• The characterization of those parameters by electrochemical means

Different Cu plating chemistries will be used as model systems.