PhD

Smart Systems and Energy Technology

• DNA analysis with a nanopore
• Reconfigurable biosensor arrays
• 3D-SOC integration by stacking heterogeneous IC technologies
• Technology aware design research
• Analog and RF circuit design for 45nm CMOS Cognitive Radio t
• CMOS design for mm-wave applications
• Cognitive radio processor architecture and platform
• Cognitive radio functionality
• Miniaturized Hyperspectral Vision System for the Embedded Do
• Multi-View Video
• Run-time resource management for dynamic Embedded Software
• Solar Cell Technology
• Organic electronics
• Wireless autonomous transducer solutions
• Ultra-high frequency communication with thin-film oxide elec

3D-SOC (System-On-Chip) integration by stacking heterogeneous IC technologies

This 3D-SOC concept is clarified in the figure below for the interconnections between a logic die and a memory die.  In a standard 2D-SiP approach, the die are connected through their standard chip-I/O pads, resulting in long, slow and power-hungry interconnect lines between a logic 'tile' and a memory 'tile' (or 'bank').  In a standard SOC approach, the memory banks are integrated directly on the chip, adjacent to the logic-tiles that interact with it.  This results in a more efficient system, at the expense of increased chip complexity and cost. Memory cells are difficult to effectively integrate in standard CMOS processes and generally result in lower density and performance than dedicated memory technologies.  The 3D-SOC allows the use of standard, optimal memory technology in combination with standard CMOS logic die.  A high-density 3D interconnectivity ensures the interconnectivity between the logic tiles and the memory banks, avoiding long interconnect lines. This concept can be expanded to include more than two layers of die.

 
For the realisation of 3D-SOC several technology options may be chosen.  Both die to wafer and wafer-to-wafer bonding techniques may be used.  Technologies need to be developed for ultra-fine flip chip interconnect technologies, die thinning down to the active silicon layer as well as very small low resistance through hole vias with diameters below 5 micron.
This work is highly interdisciplinary as it requires technology know-how, study of the impact on the die thinning process on the electrical functionality of the devices, characterisation of the electrical characteristics of 3D interconnects and interfacing with system-level design methodologies for 3D-SOC.