At today’s IEEE International Electron Devices Meeting, IMEC presents the potential of copper contact technology for the (sub-)32nm node which has clear advantages for performance and power consumption. Using the proper copper contact barriers will be key to guarantee reliability and yield of the CMOS front-end.

From the 32nm CMOS node onwards, contact size scaling is expected to deteriorate the transistor performance by increased contact resistance. IMEC is therefore developing a technology in which the conventional tungsten plugs are replaced by a copper contact filling technology.

First copper contact filling results demonstrated on 150nm contact sizes show a 50% reduction in contact resistance without increased diode leakage. The technology has been validated by loaded ring oscillator performance achieving the same delay as with conventional tungsten plugs at 60% power reduction. These results show that the introduction of copper at the contact level offers clear advantages for circuit performance and power dissipation, which is believed to be even more effective in future technology nodes from 32nm and below.

First reliability data for this copper contact technology are presented at today’s IEDM conference. A detailed electrical and failure analysis of copper related front-end yield and reliability challenges in integrated technology showed that if the Cu barrier process is marginal, device failure rapidly occurs.

The choice of a good barrier will be imperative for reliability and yield. Devices with poor copper barrier quality however suffer from leaky junctions, broken gate dielectrics and reduced time to breakdown. In the absence of an appropriate barrier, copper diffuses out of the plug into the silicon and forms copper silicide. Copper silicide penetrates deeper in p+ regions than into n+ regions causing leaky p+ diodes by junction spiking while the n+ diodes remain intact. Nevertheless, in transistor structures, where both PMOS and NMOS are used, lateral diffusion of copper can cause spiking through a nearby extension region and through the gate dielectric giving rise to high junction and high gate leakage.

These results were obtained within IMEC's core program on (sub-)32nm CMOS, which joins forces from nine of the world's leading IC manufacturers or foundries (Infineon, Intel, Micron, NXP, Panasonic, Samsung, STMicroelectronics, Texas Instruments and TSMC).

For more information:

Katrien Marent
Corporate Communication Manager
IMEC, Kapeldreef 75
B- 3001 Leuven, Belgium
Tel +32 16 28 18 80 Fax +32 16 28 16 37
Email: Katrien.Marent@imec.be