Scaling-driven nanoelectronics

3D integration: design and architecture of 3D ICs

• 3D systems-in-a-package
• 3D wafer-level packaging
• 3D stacked IC and 3D IC
• 3D design
• Packaging reliability

3D SIC and 3D IC technologies use foundry-level integration to stack thinned ICs. In 3D SIC, the 3D interconnects are realized at the global or intermediate level of the chip wiring hierarchy. For 3D ICs, interconnects are local, requiring submicrometer through-Si via connections.

Invent - Imec is developing die stacking with through-die interconnects with a density of up to 10,000 interconnects per mm2. Cu vias are realized in a single damascene process, after front-end and contact processing, but before processing back-end metallization layers. This enables via diameters of 1-5μm.

Achieve - In 2008, Imec reported a first-time demonstration of 3D integrated circuits obtained by die-to-die stacking and using 5µm Cu through-silicon vias (TSV). The dies were realized on 200mm wafers in imec’s reference 0.13μm CMOS process with an added Cu-TSVs process.