Optical lithography is the workhorse of the IC industry since several decades. By passing light through a mask, the IC design is projected on the silicon. The mask carries a pattern, formed by areas that are either transparent or opaque for the light that is used. Where the light hits the silicon, it reacts with the resist chemicals on the wafer’s surface, effectively copying the pattern on the silicon wafer.
The smaller the wavelength of the light that is used, the finer the patterns that can be projected, and the smaller the transistors on the final chip can be made. The state-of-the-art, used to produce today’s most advanced memory and logic chips, is 193nm immersion-based lithography.
At imec, 193nm lithography is pushed to its limits, looking for techniques to produce the next technology node on time. That is necessary because alternatives – most notably EUV lithography – are still some time out.
One technique that allows 193nm lithography to print finer details is double patterning. With double patterning, you expose the silicon twice, with two masks that each print half of the lines. Because this process is expensive, we have set up a program to compare and evaluate chemicals and techniques for resist freezing, a technique to reduce its costs. In the course of this program, we have seen important progress, making double patterning a viable process, in the first place for designs with a repeated, regular geometry, such as memory ICs.
Another promising technique to push 193nm lithography is source mask optimization. Here, imec started work on diffractive optical elements and flexible illuminators. With source mask optimization, it is for example possible to tailor the illumination shape to the specific layout to be printed, improving the resolution and process margins to some extent.
More and more of imec’s lithography efforts have shifted towards developing EUV lithography. EUV lithography uses extreme UV light (13.5nm wavelength), which allows a much finer print, but which also requires new tools and techniques. Currently, imec is illuminating wafers and refining the EUV technique with the help of ASML’s EUV alpha demo tool; its successor, the EUV preproduction tool (NXE:3100), is scheduled for installation at imec at the end of 2010.
The main issue to solve with EUV has always been the power of the light source. This power, long the major obstacle, has been gradually improved, and the industry now has a roadmap to arrive at a stable high-power source needed for cost-effective industrial IC production. Finding suitable EUV resists is the second issue. Also here, in the two years that we have been working on EUV, there has been a lot of progress. We now have resists to pattern 27nm features on the alpha demo tool, and I am confident that with effort and time, suitable resists for 22nm and later on for 16nm are within reach on future exposure tools. One of the strong points of the EUV technology is that it can be extended, even towards 11nm technology.
By far the most pressing issue for EUV is formed by the masks. On the wafers that we have exposed with EUV, we see a lot of defects that originate from the masks. Imec has been one of the first to look into this issue, and we have collected and published the most relevant data. The IC industry is keenly interested in our research, because if the mask issue is not tackled, it could turn out to be a showstopper for EUV lithography.
Finally, we also started a program on alternative lithography techniques, notably maskless e-beam lithography and imprint. We started out with surveying the IC industry, which showed that there is an interest in these techniques, mainly as a backup to EUV lithography. Now we are following the players in this area. As part of our effort, we have illuminated wafers at some of these companies, allowing us to compare the results of alternative litho techniques and optical lithography on our metrology tools.